The present invention is directed to leakage current compensation for an integrated circuit (IC), and more specifically to a compensation circuit that functions over a wide temperature range.
Higher packaging densities and the expense and/or ineffectiveness of traditional techniques for removing heat (e.g., heat sinks) from electronic assemblies (e.g., integrated circuits (ICs)) has resulted in a demand for IC designs that continue to function with increasingly higher temperatures. One aspect of high temperature IC operation is the inherent current leakage that occurs across reverse-biased semiconductor junctions. While in many cases, leakage currents are negligible at low operating temperatures, leakage currents can become significant as the operating temperature increases. In bipolar analog circuitry, the greatest point of leakage is generally from the n-type epitaxial pockets which contain and isolate both NPN and PNP transistors, as well as resistors. This leakage current can result in an undesirable error in a number of applications, such as those that require low bias current conditions or the maintenance of an electrical charge, e.g., integrators and sample-and-hold circuits. For example, in the automotive field many electronic assemblies, e.g., pencil coil assemblies, are located approximate each engine cylinder, which subjects the assembly to a wide range of temperatures.
Prior art leakage compensation circuits (i.e., compensators) have usually required some component trimming for a given compensator to properly account for leakage currents. Further, component trimmed compensators have required silicon area for trim networks and access points, used to perform trimming operations, in addition to the area consumed by the compensator. In addition, most prior art compensators have been directed to metal-oxide semiconductor field-effect transistor (MOSFET) devices that have required detailed device characterization, with respect to temperature dependence of the device.
As such, what is needed is a compensation circuit that is designed to compensate for specific leakage currents, at the time of device layout, that does not require adjustment after fabrication. Further, it would be desirable if the compensation circuit accurately accounted for the leakage currents in a fashion that both matched and compensated for the temperature related characteristics of a given n-type leaking epitaxial pocket.
An embodiment of the present invention is directed to a compensation circuit for providing a compensation current to a node of an integrated circuit that experiences increased reverse-bias leakage current, between a n-type leaking epitaxial region and a p-type substrate, with increased temperature. The compensation circuit includes a p-type substrate, a n-type compensator epitaxial region, a contact region, a center p-type region and a plurality of peripheral p-type regions. The n-type compensator epitaxial region is formed on the p-type substrate. The contact region is formed into the n-type compensator epitaxial region. The center p-type region is formed into the n-type compensator epitaxial region and is surrounded by the plurality of peripheral p-type regions, which are also formed into the n-type compensator epitaxial region. At least one of the peripheral p-type regions is coupled to the contact region to serve as a reference collector. Any remaining peripheral p-type region is coupled to the node of the integrated circuit that is experiencing increased reverse-bias leakage current to serve as a node collector and provide the compensation current. The compensation current provided is substantially determined by the ratio of the total peripheral surface area facing the center p-type region associated with the node collector and the total peripheral surface area facing the center p-type region associated with the reference collector and is also determined by the total surface area of the n-type compensator epitaxial region.